1. Field of the Invention
The invention relates to metal-oxide-semiconductor field effect transistor (MOSFET) circuit design and more particularly to circuit configurations for reducing leakage current pathways.
2. Background
Advances in semiconductor manufacturing technology have resulted in substantially reducing the physical dimensions of transistors such as MOSFETs. In turn this has led to ever-increasing numbers of these physically smaller transistors being incorporated into integrated circuits.
As MOSFET transistor geometries have shrunk, it has been necessary to reduce the thickness of the gate insulator layer in order to achieve the desired electrical characteristics from the smaller, typically submicron, transistors. However, reducing the thickness of the gate insulator has also required a reduction in the operating voltage of circuits built with these transistors. The reduced operating voltage is necessary to avoid having an electric field across the gate insulator large enough to damage the gate insulator and thereby create a malfunctioning device.
With continued reduction of power supply voltage for deep submicron MOSFET circuits, the threshold voltages of both n-channel field effect transistors (NFETs) and p-channel field effect transistors (PFETs) have to be reduced correspondingly in order to maintain acceptable current drive in these transistors.
Unfortunately, deep submicron FETs with threshold voltages on the order of a few tenths of a volt, tend to suffer from an undesirable amount of subthreshold leakage current.
What is needed are methods and circuits for reducing leakage current in MOSFET circuits.